Integrated circuits are designed with ever-decreasing power supply (VCC) voltage levels. Nevertheless, certain types of circuitry, such as flash memory cells, may require input voltage levels with relatively high magnitudes. Charge pump circuits may be used to provide such high voltage levels in integrated circuitry powered by relatively low power supply levels. For example, Pelliconi et al., “Power Efficient Charge Pump in Deep Submicron Standard CMOS Technology,” Proceedings of the 27th European Solid-State Circuits Conference, 18-20 Sep. 2001, and U.S. Patent Publication No. 20030214346 (Pelliconi), the teachings of both of which are incorporated herein by reference, describe positive-voltage and negative-voltage charge pumps that can provide voltage levels having magnitudes greater than the available power supply levels. These charge pumps are implemented using triple-well devices. However, negative voltage charge pumps of this type suffer from back-body effects in which the transistors fail to conduct properly at certain power supply levels.